Today's embedded applications are extremely complex
with a single microcontroller handling multiple functions.
These applications demand enhanced safety and opti-
mal execution time with real-time response, along with
seamlessly synchronizing various functions. From motor
control with integrated power factor correction to handling
light intensity, complex applications require switching
among various modules with ease. Processor driven tim-
ing and sequencing solutions are subject to inherent la-
tencies, which cannot always be accurately predicted.
This approach also consumes precious CPU bandwidth,
under-utilizing its capabilities, which could be off-loaded
to optimize the application performance. The Peripheral
Trigger Generator (PTG), a Core Independent Peripheral
(CIP), featured in Microchip's 16-bit dsPIC33 Digital Sig-
nal Controller (DSC) devices, enables precise timing and
sequencing of functions in complex applications to be
coordinated, while off-loading the CPU. Several exam-
ples are detailed to showcase how the PTG helps to
streamline peripheral sequencing for timing-critical ap-
plications such as controlling a motor with power factor
correction, controlling the intensity of light or generating
a constant frequency signal which also acts as a clock
source independent from the core. Since the PTG is core
independent, this work can be done while the CPU sleeps
to save power or focuses on other critical tasks.
As the name suggests, the PTG is a user-programmable
sequencer that generates triggers with complex input signal
sequences to coordinate the operation of other on-chip pe-
ripherals. Applications that use the PTG do so with other
peripherals, such as an Analog-to-Digital Converter (ADC),
Output Compare (OC), Pulse-Width Modulator (PWM), tim-
ers and interrupt controllers to achieve a complex sequence
of triggers and responses. The PTG not only reduces the
application dependency on the core but also solely takes
care of module interactions, which helps to reduce software
complexity and maintain modularity.
The PTG peripheral supports 8-bit commands, called the
step commands, to the PTG queue registers. Each 8-bit step
command is comprised of a 4-bit command code and a 4-bit
option field. These commands define a sequence of events
for generating output trigger signals to the peripherals. The
step commands can also be used to generate interrupt re-
quests to the core.
Power factor and motor control
In an integrated Power Factor Correction (PFC) and mo-
tor control application, a single DSC controls a permanent
magnet synchronous motor using a Field Oriented Control
(FOC) scheme as well as the PFC converter. This applica-
tion requires three PWM channels to control the motor
functioning and an additional PWM to control the PFC op-
eration. An Output Compare (OC) peripheral can be used
to augment the number of PWM channels available to the
application, even beyond the number of high-speed PWM
channels available on the device.
The PWM peripheral together with an OC peripheral can be
used to generate the necessary signals for motor control and
PFC operation. However, in an application such as PFC, exe-
cution timing is very important making it necessary to com-
plete various tasks within an optimal execution time. These
include synchronising motor control and PFC PWM, trigger-
ing ADC for conversion and switching ADC channels used for
motor control and PFC feedback signals.
These requirements can be achieved effectively using the
PTG peripheral, which can synchronise the high-speed
PWM and OC peripherals and generate ADC peripheral trig-
gers by monitoring high-speed PWM peripheral edges. It
also monitors the "ADC conversion done" interrupt and gen-
erates appropriate interrupts, executing the FOC and digital
PFC control code. And it reduces CPU intervention, making
the peripheral handling core independent. This reduces the
overall power consumption of your application while freeing
up the CPU to perform more critical functions. The switching
frequency of motor control and PFC PWM should be select-
ed such that it is in integral multiples.
The ADC in the dsPIC® DSC is capable of four-channel
simultaneous sampling. Both FOC and PFC algorithms have
their own analog channels that need to be sampled simulta-
neously, because the phase relationship of these signals is
key to implementing efficient control.
Pulling the Peripheral Trigger
Ravikiran Shetty, Microchip Technology
The feedback signals of the motor control and PFC should
be selected such that, by alternating between the ADC chan-
nel selections, both motor control and PFC signals are sam-
pled. The motor control and PFC signals can be connected
to the sample-and-hold (S&H) circuits before triggering the
ADC, based on the edges of the PWM. The channels should
be configured in such a way that, at the end of a four-chan-
nel sample and conversion sequence, the conversion re-
sults for either FOC or PFC are available in their correspond-
ing ADC buffer registers.
After setting the channel selection bits to connect the
PFC feedback signals to the S&H circuit of an ADC, for
every PFC PWM cycle, a trigger has to be generated. Sim-
ilarly, for every motor control PWM cycle, an ADC trigger
has to be generated after setting the channel selection bits
to connect the motor control feedback signals to the S&H
circuit of the ADC. Hence, the PTG peripheral is config-
ured to generate an ADC trigger by monitoring the edges
of the motor control and PFC PWM pulses. In addition, two
PTG interrupts are generated to execute the code for FOC
and PFC, as shown in Fig. 1.
As seen in this example, a PTG simplifies the implemen-
tation by efficiently sequencing the use of the ADC and
PWMs to achieve motor control and PFC implementation in
one dsPIC33 device.
In a light intensity control application, a PWM generator
using an OC can be used to control the brightness of a light.
In this application, two OC peripherals are used and their
duty cycles are controlled by inputs obtained from two sepa-
rate ADC channels. Depending on each ADC value, the duty
cycle is updated. The PTG peripheral supports a simpler
way of synchronising ADC and OC peripherals. In addition,
the PTG helps avoid a peripheral deadlock to enhance ap-
To perform synchronisation, the circuit first monitors the
ADC and generates appropriate interrupts to change the
OC duty cycle. It then changes the ADC channel without
disturbing the CPU, as the PTG can do this independent-
ly. As an additional safety feature, in the event of an un-
expected failure, the PTG peripheral has a dedicated
watchdog timer to monitor and perform the necessary re-
quired corrective actions. A block diagram of this appli-
cation is shown in Fig. 2.
The watchdog timer within the PTG peripheral will pre-
vent a situation where the PTG waits indefinitely for an
external event when executing a command that waits
for a hardware trigger high-low state. In this applica-
tion, the PTG will wait for an ADC-conversion-done trig-
ger. Once enabled, the watchdog timer starts counting
when the command execution starts. It is disabled when
the command completes execution. If an expected
event fails to arrive before the watchdog timer time-out
period expires, the PTG peripheral aborts the failing
Applications that are made easier by using a peripheral trigger generator
command underway and halts the sequencer. It then
issues a watchdog timer error interrupt to the CPU.
This acts as a safety feature to recover from a situation
where the ADC or PTG peripheral stops working. These
peripherals can be re-initialized and restarted within the
watchdog timer error interrupt.
The PTG will make the application core independent by
switching the ADC channels and monitoring peripherals
without the CPU peripheral's intervention. This enables the
CPU to be used for other tasks in the application.
The PTG alone will take care of all interactions within a
peripheral, which helps reduce software complexity and
maintain modularity. The PTG peripheral's watchdog timer
will help recover from any catastrophic failure, thereby pro-
viding a more robust application.
Constant frequency waveform
A PTG peripheral can be used to generate a constant
frequency signal which also acts as a clock source. The
PTG triggers a comparator which acts as a mask input
select. The PTG's trigger pulse width can be varied and
the PTG has its own timer. The peripheral trigger can
also work as a mask input select for the op amp and
comparator, as shown in Fig. 3.
Using this feature, a PTG output can be brought out
through a comparator peripheral. The comparator is con-
figured such that the inverting input is connected to
ground and the non-inverting input is connected to an
internal reference voltage.
The trigger pulse will directly emerge as the comparator out-
put. As long as the PTG generates triggers continuously, the
comparator will generate a constant frequency waveform. The
pulse width of the waveform will be one cycle of the PTG clock.
The on-off times can be controlled by the PTG timer and
pulse-width bits. The output pulse width will decide the off
time of the output waveform and the timer will decide the on-
time of the output waveform, which is the delay between the
triggering comparator peripherals.
Depending on the comparator output polarity, the on-off
time will be controlled by either the timer or pulse-width bits.
The output frequency can also be controlled by a register
that acts as a clock divider.
By changing the comparator output polarity, a complemen-
tary waveform can be generated using four comparator pe-
ripherals. The width of the pulse can be modified using the
pulse-width bits, which reduce the frequency of the output.
Hence, a constant waveform can be generated using the
PTG and comparator peripherals.
Among the advantages of using the PTG in this applica-
tion are that the output can act as a constant clock source
and run completely independent of the core. Using more
comparator peripherals, an even complementary waveform
can be generated. The PTG also works in power-saving
modes such as idle and sleep.
The PTG peripheral in Microchip's dsPIC33 Digital Sig-
nal Controller devices lets users design complex applica-
tion sequences with increased flexibility for timing-critical
or power-critical applications. A PTG allows various pe-
ripherals to interact with each other with little to no CPU
interruption and enhances the capabilities of the existing
peripherals, thus expanding the possibilities of what any
given peripheral can accomplish.
Using a PTG peripheral provides faster response time and
reduced software burden. The peripheral also provides built-
in functions, such as a dedicated watchdog timer, that in-
crease functional safety.
Fig. 1: Code execution using PTG interrupts
Fig. 3: User-programmable masking function
Fig. 2: Output Compare duty cycle control