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The continued adoption of digital control in power con-

version and distribution is accredited to the flexibility and

increased efficiency it delivers. However, these gains do

not come free; they are the result of complex and so-

phisticated algorithms working at increasingly higher pro-

cessing speeds in order to optimize the efficiencies of

switching power supplies.

The optimisation of switch-mode power supplies is in-

creasingly seen as a significant opportunity for manufac-

turers to deliver more efficiency in end-products. The

challenge, however, is maintaining that efficient opera-

tion across a wide and varying array of load conditions.

The introduction of Power Factor Correction introduced

a new age of efficiency targets - both regulatory and mar-

ket-driven - and it has become a major focus for semi-

conductor providers, striving to continually improve their

solutions to digital power control. Software-based algo-

rithms provide the potential for more flexible and effi-

ciency solutions, when coupled to the right hardware.

Digital Control

Power conversion invariably starts with an AC

source, which is then rectified to DC and further

stepped down through various intermediate voltages

until eventually reaching the Point of Load (POL). The

Power Factor of a system is the ratio between the true

and apparent power; the closer to unity the ratio the

more efficient the system. Power Factor Correction

(PFC) is the method employed to restore the ratio to

unity (or as close as possible) and may be achieved

using capacitors, but it is increasingly viable to apply

PFC using Buck, Boost or Buck/Boost conversion un-

der digital control. Moving between the analog and dig-

ital domains typically adds additional latency; the con-

trol loop delay, and it describes the total time taken to

apply a change to the conversion and measure the ef-

fects of that change. Under steady-state conditions this

would be relatively simple but under variable loads the

speed with which the control loop executes directly in-

fluences the PFC and overall efficiency.

The challenge increases when the POL stage requires

low voltage but high current levels, as is often the case

in modern embedded systems. Today, microprocessors,

FPGAs and ASIC invariably operate from low voltages -

3.3V and below - but require much higher current in or-

der to meet their overall power demands. Furthermore,

the demands will vary significantly based on the operat-

ing requirements. As shown in Figure 1, the use of digi-

tal control can be applied throughout the entire power

conversion flow in order to introduce not only greater

efficiency but the flexibility to sustain that efficiency

across a wide range of loads.

This is enabled though the continued development of

sophisticated algorithms, including adaptive algorithms

that can react to changes in load levels, and non-linear

and predictive algorithms that can improve the dynam-

ic response under transient conditions. And as semi-

conductor technology develops, manufacturers are

able to employ this to increase the performance of dig-

ital control solutions, allowing higher switching frequen-

cies that result in not only greater efficiency but higher

power density.

Digital Signal Controllers

The emergence of digital control in areas such as pow-

er conversion, motor drives and similar applications

where adaptive control is advantageous, has led to the

development of Digital Signal Controllers (DSCs). These

devices merge the benefits of a Digital Signal Processor

(DSP); extensively used in audio and video processing,

and the venerable Microcontroller (MCU), to create a

new class of device perfectly tuned to executing control

algorithms that would be too complex for a traditional

MCU, with the peripherals and interfaces not typically

present in a DSP.

The Next Generation in Digital

Power Supply Control

Digital control in power conversion continues to develop, thanks to the latest improvements in both

the analog and digital domains

Tom Spohrer, Microchip Technology

There is an increasing number of DSCs on the market,

all of which strive to deliver on these demands. Those

that best deliver exhibit a continued roadmap of archi-

tectural improvement, which allow developers to further

improve the speed and accuracy of the control loop in

their application, and enable them to take full advantage

of the latest developments in control algorithms.

DCSs are essentially the definitive mixed-signal solu-

tion; they must combine digital processing with analog

peripherals. Achieving an overall solution requires both

domains to function together seamlessly, which is why

fully integrated devices offer the best approach. Com-

bining both analog and digital technology on a single

device can, however, introduce design compromises, but

improving performance in both domains in a balanced

way is critical in delivering better solutions. The essen-

tial components of a DSC are a core capable of efficient-

ly executing signal processing algorithms, coupled with

signal conversion in the form of one/multiple Analog/Dig-

ital Converters (ADCs), along with some form of Pulse

Width Modulation (PWM) output used to drive power

transistors such as MOSFETs in the Buck/Boost con-

version circuit(s). Bringing these elements together in a

single architecture that supports fast control loops is the

key to building a successful DSC, which in turn is the

heart of efficient AC/DC and DC/DC power conversion.

Mixed Signal Solution

The Third Generation of Microchip’s dsPIC33 GS fam-

ily, the dsPIC33EP GS, delivers increased performance

in these critical areas over the Second Generation. The

core now delivers 70MIPS (up from 50MIPS) but also

includes features such as context-selected working reg-

ister sets that further increase performance for digital

power applications beyond what the increased raw MIPS

rating might suggest. By adding two additional working

register sets the core now supports almost instanta-

neous context switching. The performance of the analog

peripherals has also been improved relative to previous

generations. For example, products in this family offer

up to five 12-bit ADCs, with the ADC conversion latency

reduced from 600ns to 300ns. Together, these improve-

ments enable a three-pole-three-zero compensator la-

tency to be reduced from around 2ìs to less than 1ìs

thereby reducing phase erosion to improve stability.

Faster control loops also allow for higher switching fre-

quencies and better transient response. The resulting

efficiency gains made possible by the increased perfor-

mance also lead to increased power density; power sup-

plies can be designed to be smaller, using fewer and

smaller discrete passive components.

A further architectural improvement in the “GS” is the

introduction of dual Flash partitions, supporting a feature

known as Live Updates. This allows a control algorithm,

or any other software executed by the DSC, to be updat-

ed in the field while the power supply remains fully oper-

ational; the new software is loaded in to the second, non-

operational, Flash partition and, when verified, the core

switches to executing from the second Flash partition.

This is a feature that is particularly welcome in high-avail-

ability applications, such as server power supplies,

where even small efficiency gains can result in large re-

ductions in operational costs. Without the live update

feature, such applications would be left with either up-

dating the software during scheduled (or unscheduled)

maintenance breaks in operation, or leaving the code

unmodified and missing out on the potential benefits.

Both of these options would be unwelcome in the server

environments, of course.


The digital control of power conversion continues to

develop, progressively replacing analog control due to

the flexibility and potential efficiency gains it presents.

While the complexity is undoubtedly a consideration for

developers, the benefits can be persuading. Regulatory

requirements aside, the use of digital control can clearly

deliver better power conversion solutions and, with the

introduction of Live Update, offer an upgrade path for

solutions already deployed - even in high availability ap-


DSCs represent the pinnacle of digital control in this

and many other applications where complex algorithms

meet high performance analog peripherals. The “real

world” of mixed signal solutions continue to offer an op-

portunity for performance gains at every level; fully inte-

grated, advanced programmable solutions like the

dsPIC33EP GS family represent the leading-edge of

DSC technology, and will provide power supply devel-

opers with the next generation in control.

Figure 1. Detailed SMPS AC/DC reference design block diagram